Enum InstructionSet 

#[non_exhaustive]
#[repr(u8)]
pub enum InstructionSet {
    Scalar = 0,
    Unknown = 1,
    X86V1 = 2,
    X86V2 = 3,
    X86V3 = 4,
    X86V4 = 5,
}

Enum of supported instruction sets

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

Scalar = 0

Scalar (no SIMD)

Unknown = 1

Unknown ISA, usually the result of register emulation, such as with Glam vectors as registers.

X86V1 = 2

Available on x86 or x86-64 only.

x86/x86_64 SIMD instruction set level 1 (SSE2)

X86V2 = 3

Available on x86 or x86-64 only.

x86/x86_64 SIMD instruction set level 2 (SSE4.2 + POPCNT)

X86V3 = 4

Available on x86 or x86-64 only.

x86/x86_64 SIMD instruction set level 3 (AVX2 + FMA)

X86V4 = 5

Available on x86 or x86-64 only.

x86/x86_64 SIMD instruction set level 4 (AVX-512F)

Implementations

impl InstructionSet

pub fn get() -> InstructionSet

Available on x86 or x86-64 only.

Detect the current instruction set at runtime. This result is cached for future calls.

pub const fn min(a: InstructionSet, b: InstructionSet) -> InstructionSet

Order two sets by capability, returning the weaker.

Ordering is the enum’s declaration order, which ascends by capability within an architecture (Scalar < X86V1 < .. < X86V4). Across architectures it is meaningless, but two architectures’ variants never coexist, since each is cfg-gated to its own target.

pub const fn max(a: InstructionSet, b: InstructionSet) -> InstructionSet

Order two sets by capability, returning the stronger. See min.

pub const fn assert_eq(a: InstructionSet, b: InstructionSet) -> InstructionSet

Assert two sets are the same, returning it. Compares discriminants because PartialEq is not callable in a const fn.

pub const fn has_instruction_level_parallelism(self) -> bool

Whether the target executes independent instructions in parallel, so that breaking a dependency chain into several accumulators pays off.

A property of the hardware, not of the instruction set: a superscalar CPU reorders scalar code just as happily as SIMD code, so this does not vary by variant. SIMT targets (SPIR-V) hide latency with occupancy instead and gain nothing from extra accumulators.

impl InstructionSet

pub const fn num_registers(self) -> usize

Estimate of how many SIMD registers the ISA exposes. Used by inlining/unrolling heuristics. See also NativeIsa::Registers, the type-level equivalent.

pub const fn has_fma(self) -> bool

Whether the ISA has a true fused multiply-add (one rounding).

pub const fn is_simd(self) -> bool

Whether the ISA is actually SIMD. False for Scalar, Unknown, and SPIR-V (which is SIMT: one lane per invocation).

pub const fn unaligned_is_cheap(self) -> bool

Whether unaligned loads/stores cost about the same as aligned ones, so an unaligned iterator need not be avoided.

pub const fn unroll_factor(self) -> usize

Suggested unroll factor for bulk loops, scaled to the register file: more registers allow more accumulators in flight.

pub const fn has_masked_operations(self) -> bool

Whether the ISA has first-class masked operations (AVX-512 opmask registers), letting the _c/_m/_z variants lower to a single instruction instead of a blend.

Trait Implementations

impl Clone for InstructionSet

fn clone(&self) -> InstructionSet

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for InstructionSet

impl Debug for InstructionSet

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for InstructionSet

impl Hash for InstructionSet

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for InstructionSet

fn cmp(&self, other: &InstructionSet) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized,

Restrict a value to a certain interval.

fn clamp_to<R>(self, range: R) -> Self

where Self: Sized, R: ClampBounds<Self>,

🔬This is a nightly-only experimental API. (clamp_to)

Restrict a value to a certain range.

impl PartialEq for InstructionSet

fn eq(&self, other: &InstructionSet) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl PartialOrd for InstructionSet

fn partial_cmp(&self, other: &InstructionSet) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl StructuralPartialEq for InstructionSet